1. Field of the Invention
The present invention relates to an analogue delay circuit.
2. Description of the Related Art
Delay circuits employing the charge and discharge time of capacitance and not requiring synchronizing signals (an analogue delay circuit) are widely used to obtain delay signals of arbitrary signals in a digital circuit.
The basic configuration of a prior-art analogue delay circuit takes the form shown in FIG. 1. Here, an input signal 301 is inputted to an inverter gate 304 made up of a p-type MOS transistor 302 and an n-type MOS transistor 303, the output of inverter gate 304 being connected to line 306. Line 306 is connected to the input of inverter gate 307 and to capacitance 305, the other electrode of which is grounded, and output signal 308, which is the desired delay signal, is obtained from the output of inverter gate 307.
To present the principles of the analogue delay circuit of FIG. 1 in more detail, when, for example, input signal 301 is of a low level (hereinafter abbreviated "L"), p-type MOS transistor 302 making up inverter 304 enters an ON state and n-type MOS transistor 303 enters an OFF state, thereby making line 306 a high level (hereinafter abbreviated "H") and output signal 308 "L." Charge is hereupon accumulated in line 306 and each electrode connected to this line, the electric potential generally being the power source potential V.sub.DD.
When input signal 301 changes to "H," p-type MOS transistor 302 enters an OFF state and n-type MOS transistor 303 enters an ON state. The charge of line 306 and each electrode connected to this line is released through n-type MOS transistor 303, the potential of line 306 drops to about the ground potential GND, and output signal 308 changes to "H." Because the time required to release the charge of line 306 corresponds to the product RC of the ON resistance R of n-type MOS transistor 303 and the capacitance C of capacitance 305, a delay time can be generated. As a result, when input signal 301 changes from "L" to "H," output signal 308 changes from "L" to "H" after the delay time.
Here, the ON resistance value R of n-type MOS transistor 303 changes according to the voltage inputted to the gate, the ON resistance value R becoming large when the voltage inputted to the gate is low. In other words, the delay time obtained by this analogue delay circuit varies with the change in the power-source voltage V.sub.DD.
As one means of solving this problem, an analogue delay circuit such as shown in FIG. 2 has been proposed. Analogue delay circuit 401 and 402 are analogue delay circuits such as explained in FIG. 1 but the operating power-source voltage for obtaining the desired delay time differs.
Variations in delay time due to changes in the power-source voltage can be suppressed by adding switches 404 and 405 for selecting the output of one analogue delay circuit according to the power-source voltage and a switch control circuit 403 for controlling these switches.
In order to prevent variations in delay time caused by changes in the power-source voltage, delay circuits according to the above-described prior art necessitate a plurality of analogue delay circuits as well as circuits for switching these circuits according to power-source voltage, and such circuits therefore entail the drawback of enlarged circuit scale. In particular, circuits having a wide range of operating power-source voltages have been impractical due to the necessity for numerous delay circuits.